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TPS658620ZQZT датащи(PDF) 51 Page - Texas Instruments |
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TPS658620ZQZT датащи(HTML) 51 Page - Texas Instruments |
51 / 104 page ![]() 3.48 INTEGRATED SUPPLY SEQUENCING – SUPPLY ENABLE CONTROL TPS658620 Advanced Power Management Unit www.ti.com SLVS993 – OCTOBER 2009 The default status (ON or OFF) of each rail is shown in Table 3-17. If the default for a supply rail is ON the trigger group associated to the supply determines the control signal that initiates the delay time to the start of the rail power up. There are four trigger groups, one internal and three external pins: INTERNAL This group is controlled by an internal signal that goes high when the TPS658620 goes from the RTC_ON state to the SUPPLYSEQ state. SM0EN This group is controlled by the falling edge of the SM0EN pin and starts when the pin voltage is below its VIL level. SM1EN This group is controlled by the rising edge of the SM1EN pin and starts when the pin voltage is above its VIH level. SYNCEN This group is controlled by the rising edge of the SYNCEN pin and starts when the pin voltage is above its VIH level. The trigger group of each rail and its associated delay is shown in Table 3-17. If a supply rail has a default state of ON and the appropriate trigger is high, the rail will be turned on after the delay time for that rail has expired. The delay time starts when the trigger signal for that supply has gone high, while SUPPLYSEQ state is set. No delays are available after NORMAL mode is set. Table 3-17. TPS658620 Integrated Supply Power-Up Defaults TPS658620 SETTINGS DEFAULT DEFAULT SUPPLY TRIGGER DELAY STATE VOLTAGE LDO0 OFF 3.3V SM1EN 3.75ms Value applies to LDO0, LDO1 LDO1 ON 1.1V SYNCEN LDO2 ON 1.2V INTERNAL 0ms Value applies to LDO2, LDO3 LDO3 OFF 3.3V SM1EN LDO4 ON 1.8V INTERNAL 3.75 ms LDO6 ON 3.3V SYNCEN 15ms LDO7 OFF 3.3V INTERNAL Value applies to LDO6, LDO7 and LDO8 LDO8 OFF 2.85V SYNCEN LDO5 ON 2.85V SYNCEN 3.75ms Trigger applies to both LDO5 and LDO9 Value applies to LDO5, LDO9 LDO9 OFF 2.85V SM0 ON 1.2V SM0EN 2.5ms SM1 ON 1.0V SM1EN 2.5ms SM2 OFF 4.4V INTERNAL 15ms The ON or OFF mode for each supply is defined by the supply enable RAM control bits and enable pins SM0EN, SM1EN and LDO4EN. The supply enable bits are located in registers SUPPLYENA, SUPPLYENB, SUPPLYENC, SUPPLYEND, SUPPLYENE (see supply functional description for more details). The functionality of the RAM bits and enable pins is dependent on the state set in the state machine as follows: When the NORMAL state is NOT set : The pins SM1EN , SM0EN and LDO4EN will always control the ON or OFF modes for all supplies that use them as triggers. The supply enable RAM bits will control the ON or OFF modes for the supplies. When the NORMAL state is set: The supply enable RAM bits will always control the ON or OFF modes for the supplies. The pins SM1EN, SM0EN and LDO4EN may control the ON or OFF modes for supplies SM1, SM0 and LDO4. The enable pins do not control the ON or OFF modes of any other supplies. Submit Documentation Feedback DETAILED DESCRIPTION 51 |
Аналогичный номер детали - TPS658620ZQZT |
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Аналогичное описание - TPS658620ZQZT |
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