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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TPS658620ZQZT датащи(PDF) 28 Page - Texas Instruments |
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TPS658620ZQZT датащи(HTML) 28 Page - Texas Instruments |
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28 / 104 page  3 DETAILED DESCRIPTION 3.1 I 2C INTERFACE 3.2 I 2C ADDRESS 3.3 DVM REGISTER ACCESS 3.4 SCLK/SDAT AND PSCLK/PSDAT TIMEOUT 3.5 I 2C BUS RELEASE 3.6 I 2C BUS ERROR RECOVERY TPS658620 Advanced Power Management Unit SLVS993 – OCTOBER 2009 www.ti.com Two I2C configurations are implemented in the TPS658620 device: A –Standard I2C interface (SDAT/SCLK engine) : A single I2C communication port provides a simple way for an I2C compatible host to access system status information, reset fault modes, and set supply output voltages. The I2C port functions as a SLAVE enabling I2C compatible hosts (MASTER) to perform WRITES and READS to/from internal registers. The I2C port is a 2-wire bidirectional interface using the SCLK (clock) and SDAT (data) pins. The I2C is designed to operate at SCLK frequencies up to 400 kHz. The standard 8 bit command is supported. The CMD part of the sequence is the 8 bit register address to read or write. B – Power I2C interface (PSDAT/PSCLK engine): The TPS658620 supports processors that use a dedicated I2C bus to dynamically adjust critical supply voltages by adding a second I2C bus (Power I2C) connected to a second, dedicated I2C engine. The Power I2C port is a 2-wire bidirectional interface using the PSCLK (clock) and PSDAT (data) pins. The Power I2C is designed to operate at PSCLK frequencies up to 400 kHz. A multiple-byte data-register pair command protocol, not compatible with the standard I2C protocol, is supported by the Power I2C engine. The Power I2C engine does not support read operations. NOTE The Standard and Power I 2C engines are always reset by the sequencer when the TPS658620 is in the POWER-UP state and when the SLEEP state is set. The TPS658620 will acknowledge (ACK) addresses 0x68 (writes) and 0x69 (reads) and will NACK any other address. The sequencer state machine disables write access to specific supply voltage setting registers when the TPS658620 is initially powered and when the integrated supplies are being sequenced. See the sequencer functional description for details. The TPS658620 monitors the SCLK/PSCLK clock lines, and it identifies a timeout condition if the clock line is held at a logic low for longer than 30ms. The I2C engine is NOT reset when the clock line timeout is identified. The TPS658620 monitors the SDAT/PSDAT data lines. The I2C engine will be reset when the data line is held at a logic low for more than 30ms. The TPS658620 I2C engine does not create START or STOP states on the I2C bus during normal operation. The I2C bus specification does not define a method to be used when recovering from a host side bus error. During a read operation the SDAT pin can be left in a LO state if the host has not sent enough SCLK pulses to complete a transaction (i.e. host side bus error). The TPS658620 will clear any SDAT LO condition if 10 SCLK pulses are sent by the host, enabling recovery from host side bus error events. DETAILED DESCRIPTION 28 Submit Documentation Feedback |
Аналогичный номер детали - TPS658620ZQZT |
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Аналогичное описание - TPS658620ZQZT |
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