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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TPS658620ZQZR датащи(PDF) 4 Page - Texas Instruments |
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TPS658620ZQZR датащи(HTML) 4 Page - Texas Instruments |
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4 / 104 page  2.3 ELECTRICAL CHARACTERISTICS TPS658620 Advanced Power Management Unit SLVS993 – OCTOBER 2009 www.ti.com over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT QUIESCENT CURRENT – V(BAT) = 4.2V NO EXTERNAL LOADS AT SYS PIN OR SUPPLY OUTPUTS Quiescent current, 6586x in normal or sleep IQ(ON) Power path active, control logic in low power mode (1) 375 µA mode. All supplies, peripherals and charger off IQ(DIGITAL) Quiescent current, control logic Control logic in high power mode (2) 716 870 µA SM0, SM1: enabled, PFM mode, from SYS pin 14 25 µA SM2: enabled, PFM mode, from SYS pin 19 32 µA IQ(SMn) SM0, SM1, SM2 operating quiescent current SM0, SM1, SM2: enabled, PWM mode, from VINSMn pin 6 mA 1 µA disabled via I 2C I(LDOx) = no external load 24 29 µA I(LDOx) = –1 mA 24 150 µA LDO quiescent current, All but one LDOx IQ(LDOx) disabled I(LDOx) = –50 mA 160 µA LDO disabled, TJ = 85°C 1 3 µA SM3 enabled, not switching 15 30 µA Enabled, switching 200 µA IQ(SM3) SM3 operating quiescent current 1 µA Disabled via I 2C Conversion active 1 mA Not converting, waiting for trigger 170 µA IQ(ADC) ADC operating quiescent current 1 µA ADC disabled via I 2C RTC_OUT LDO enabled 27 45 µA IQ(RTC) RTC_OUT pin quiescent current RTC_OUT disabled via I 2C, T J = 85°C . Externally applied (3) 15 µA V(RTC_OUT) = 2 V supplies real time clock counters and xtal oscillator 32k buffer enabled, 100 pF external load 24 µA IQ(V32K) V32K supply bias current , 32k buffer enabled 8 µA Disabled via I 2C Charger enabled, termination detected 40 50 µA IQ(CHG) Charger quiescent current Charger enabled, termination disabled, charge current=0 2 mA Charger disabled 5 10 µA I 2C INTERFACE TIMING – SDA, PSDA, PSCLK, SCLK TR SCLK/SDATA rise time 300 ns TF SCLK/SDATA fall time 300 ns TW(H) SCLK pulse width high 600 ns TW(L) SCLK Pulse Width Low 1.3 µs TSU(STA) Setup time for START condition 600 ns TH(STA) START condition hold time after which first 600 ns clock pulse is generated Pull-up resistors connected to 2.2V TSU(DAT) Data setup time 100 ns TH(DAT) Data hold time 0 ns TSU(STOP) Setup time for STOP condition 600 ns T(BUF) Bus free time between START and STOP 1.3 µs condition FSCL Clock Frequency 400 kHz I 2C BUFFERS – SDA, PSDA, PSCLK, SCLK VIL(I2C) Low level input voltage 0.4 V VIH(I2C) High level input voltage 1.15 V VOL(I2C) Low level output voltage SDA, PSDA configured as output, IOL=3mA 0.4 V IO(I2C) Maximum load current SDA, PSDA configured as output 8 mA ILKG(I2C) Input current V(pin)=5V or 0V 1.0 µA CI2C Input pin capacitance SDAT, SCLK, PSDAT, PSCLK pins 10 pF CI2CBUS SDAT, SCLK, PSDAT, PSCLK 400 pF I 2C bus capacitance (1) Control logic in low power mode when all functions are off and no I2C communication is on going (2) Control logic in high power mode when one of the following events happen: 6586x in power-up/rtc/rtc_on/supplyseq states, any converter in PWM mode, SM3 enabled, PWM driver enabled, ADC conversion on-going, I2C communication on-going, voltage transition for DVM supplies on-going, charger on, AC or USB supply detected, initial power-up cycle. (3) External voltage supplied by supercap or coin cell connected to RTC_OUT pin, see application diagram for details. Electrical Specifications 4 Submit Documentation Feedback |
Аналогичный номер детали - TPS658620ZQZR |
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Аналогичное описание - TPS658620ZQZR |
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