AT89C5122D-RDRUM datasheet(157/208 Pages) ATMEL

157 / 208 page

157

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Interrupt System

Introduction

The AT83R5122, AT8xC5122/23 implements an interrupt controller with 15 inputs but

only 9 are used for :

–

two external interrupts (INT0 and INT1)

–

two timer interrupts (timers 0, 1),

–

the UART interface

–

the SPI interface

–

the keyboard interface

–

the USB interface

–

the Smart Card Interface.

Interrupt System

Description

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable registers (Table 98 on page 160 and Table 99 on page

161). These registers also contain a global disable bit, which must be cleared to disable

all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority lev-

els by setting or clearing a bit in the Interrupt Priority Low registers (Table 101 on page

162 and Table 103 on page 164) and in the Interrupt Priority High register (Table 102 on

page 163 and Table 105 on page 166) shows the bit values and priority levels associ-

ated with each combination.

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another

low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of higher priority level is serviced. If interrupt requests of the same priority level

are received simultaneously, an internal polling sequence determines which request is

serviced first. Thus within each priority level there is a second priority structure deter-

mined by the polling sequence.

Table 97.

Priority Level Bit Values

IPH.x

IPL.x

Interrupt Level Priority

0 (Lowest)

011

102

3 (Highest)

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