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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M38048FFHKP датащи(PDF) 269 Page - Renesas Technology Corp |
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M38048FFHKP датащи(HTML) 269 Page - Renesas Technology Corp |
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269 / 387 page  2-145 APPLICATION 2.11 Clock generating circuit Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) 2.11 Clock generating circuit This paragraph explains how to set the registers relevant to the clock generating circuit and describes an application example. 2.11.1 Relevant registers Fig. 2.11.1 Structure of CPU mode register CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM: address 003B16) 00 : Single-chip mode 01 : Not available 10 : Not available 11 : Not available b 0 1 1 2 3 4 5 6 7 Name 0 Functions At reset R W 0 : 0 page 1 : 1 page 0 1 0 0: Oscillating 1: Stopped 0 1 0 Processor mode bits Stack page selection bit Port Xc switch bit Fix this bit to “1”. Main clock (XIN- XOUT) stop bit Main clock division ratio selection bits b1 b0 b7 b6 0 0: φ=f(XIN)/2 (high-speed mode) 0 1: φ=f(XIN)/8 (middle-speed mode) 1 0: φ=f(XCIN)/2 (low-speed mode) 1 1: Not available 0: I/O port function (oscillation stopped) 1: XCIN-XCOUT oscillation function 0 |
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