M38048FFHKP datasheet(240/387 Pages) RENESAS

240 / 387 page

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APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2004

REJ09B0212-0100Z

3804 Group (Spec.H)

(5)

Writing to I2C clock control register (S2: address 001516)

Do not write data into the I2C clock control register during transfer. If data is written during transfer,

the I2C clock generator is reset, so that data cannot be transferred normally.

(6)

Switching of SCL/SDA interrupt pin polarity selection bit, SCL/SDA interrupt pin selection bit,

I2C-BUS interface enable bit

When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt

pin selection bit, or the I2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be

set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt

pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bit

ES0 is set. Reset the request bit to “0” after setting these bits, and enable the interrupt.

(7)

Process of after STOP condition generating in master mode

Do not write data in the I2C data shift register (S0) and the I2C status register (S1) until the bus busy

flag BB becomes “0” after generating the STOP condition in the master mode. It is because the

STOP condition waveform might not be normally generated. Reading to the above registers does not

have the problem.

(8)

ES0 bit switch

In standard clock mode when SSC = “000102” or in high-speed clock mode, flag BB may switch to

“1” if ES0 bit is set to “1” when SDA is “L”.

Countermeasure:

Set ES0 to “1” when SDA is “H”.

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