M38045FFHKP datasheet(227/387 Pages) RENESAS

227 / 387 page

2-103

APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

➂ Generating of RESTART condition; Transmission of slave address + read bit

Confirm correct completion of communication at ➁ before generating the RESTART condition.

After confirming correct completion, generate the RESTART condition and perform the transmission

process of “slave address + read bit”. Note that procedure because that is different from ➀’s

process.

As the same reason as ➀, write “slave address + read bit” to the I2C data shift register (address

001116) before performing to make the START condition generate. However, when writing a slave

address to the I2C data shift register in this condition, a slave address is output at that time.

Consequently, the RESTART condition cannot be generated. Therefore, follow the slave reception

procedure before those processes.

In case the arbitration lost detecting flag (AL bit, bit 3 of address 001316) is “1”, return to the

process ➀, because other master devices will have priority to communicate.

When the last received bit (LRB bit; bit 0 of address 001316) is “1”, generate the STOP condition

and make the bus release, because acknowledgment cannot be done owing to BUSY status of the

slave device specified on the SMBUS or other reasons.

Fig. 2.5.24 Transmission process of RESTART condition and slave address + read bit

AL (address 001316), bit 3 ?

0 (not detected)

0 (ACK)

S1 (address 001316)

← 000000002 (Note 1)

LRB (address 001316), bit 0 ?

1 (NACK)

(A)

← 000100012

S0 (address 001116)

← (A)

S1 (address 001316)

← 111100002

SEI (Note 2)

End

STOP condition output

Re-transmission preparation

0 (command transmission)

PIN (address 001316), bit 4 ?

CLI (Note 2)

• Slave address value write

• Bus judgment during hold

• Judgment of arbitration lost detection

• ACK confirmation

• Slave receive mode set

• Slave address read out

• Interrupt disabled

• Interrupt enabled

• RESTART condition occurrence

1 (STOP condition)

1 (detected)

Notes 1: Set to the receive mode while the PIN bit is “0”. Do not write “1” to the PIN bit.

2: In this example, the SEI instruction to disable interrupts need not be executed because this

processing is going to be performed in the interrupt processing.

When the START condition is generated out of the interrupt processing, execute the SEI

instruction to disable interrupts.

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