M38045FFHKP datasheet(198/387 Pages) RENESAS

198 / 387 page

2-74

APPLICATION

2.4 Serial interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

q Control in the slave unit

After setting the relevant registers as shown in Figure 2.4.35, the slave unit becomes the state

where a synchronous clock can be received at any time, and the serial I/O1 receive interrupt

occurs each time an 8-bit synchronous clock is received.

In the serial I/O1 receive interrupt processing routine, the data to be transmitted next is written to

the transmit buffer register after the received data is read out.

However, if no serial I/O1 receive interrupt occurs for a certain time (heading adjustment time or

more), the following processing will be performed.

1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register.

2. The data to be received next is processed as the first 1 byte of the received data in the block.

Figure 2.4.37 shows a control procedure of the slave unit using the serial I/O1 receive interrupt

and any timer interrupt (for heading adjustment).

Fig. 2.4.37 Control procedure of slave unit

Write a transmission data

Read a reception data

Within a block transfer

term?

A received byte

counter

≥ 8?

RTI

Write dummy data (FF16)

A received byte counter +1

Heading

adjustment

counter

Initial

value

(Note 3)

Serial I/O1 receive interrupt

processing routine

Timer interrupt processing

routine

Heading adjustment

counter – 1

Heading adjustment

counter = 0?

RTI

Write the first transmission

data (first byte) in a block

A received byte counter

• Confirm the received

byte counter to judge

the block transfer term.

In this example, set the value which is equal to the

heading adjustment time divided by the timer interrupt

cycle as the initial value of the heading adjustment

counter.

For example: When the heading adjustment time is 8 ms

and the timer interrupt cycle is 1 ms, set

8 as the initial value.

CLT (Note 1)

CLD (Note 2)

Push register to stack

• Push the register used in

the interrupt processing

routine into the stack.

CLT (Note 1)

CLD (Note 2)

Push register to stack

Pop registers

• Pop registers which is pushed

to stack.

Pop registers

Notes 1: When using the Index X mode flag (T).

2: When using the Decimal mode flag (D).

• Pop registers which is pushed

to stack.

• Push the register used in

the interrupt processing

routine into the stack.

M38045FFHKP датащи(PDF) 198 Page - Renesas Technology Corp

M38045FFHKP датащи(HTML) 198 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL