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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M38041FFHKP датащи(PDF) 266 Page - Renesas Technology Corp |
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M38041FFHKP датащи(HTML) 266 Page - Renesas Technology Corp |
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266 / 387 page  2-142 APPLICATION 2.9 Watchdog timer Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) Fig. 2.9.6 Control procedure Fig. 2.9.5 Relevant registers setting 2.9.4 Notes on watchdog timer qMake sure that the watchdog timer H does not underflow while waiting Stop release, because the watchdog timer keeps counting during that term. qWhen the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program. CPUM 0 b0 b7 0 0 0 WDTCON b0 b7 0 0 0 CPU mode register (address 003B16) Processor mode: Single-chip mode Main clock (XIN-XOUT): Operating Main clock division ratio: f(XIN)/2 (high-speed mode) Watchdog timer H (for read-out of high-order 6 bits) Watchdog timer control register (address 001E16) Enable STP instruction Watchdog timer H count source: Watchdog timer L underflow 1 Fix to “1” Initialization SEI CLT CLD CPUM (address 003B16) : : CLI 000X1X002 WDTCON (address 001E16) 000XXXXX2 RESET Main processing : : •All interrupts disabled •Processor mode: Single-chip mode •Main clock f(XIN): Operating •High-speed mode selected as main clock division ratio •Interrupts enabled •Watchdog timer L underflow selected as Watchdog timer H count source •STP instruction enabled |
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