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M38041FFHKP датащи(PDF) 241 Page - Renesas Technology Corp |
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M38041FFHKP датащи(HTML) 241 Page - Renesas Technology Corp |
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241 / 387 page ![]() 2-117 APPLICATION 2.5 Multi-master I2C-BUS interface Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 3804 Group (Spec.H) 2.5.8 Notes on programming for SMBUS interface (1) Time out process For a smart battery system, the time out process with a program is required so that the communication can be completed even when communication is interrupted. It is because there is possibility of extracting a battery from a PC. The specifications are defined so that communication has been able to be completed within 25 ms from START condition to STOP condition and within 10 ms from the ACK pulse to the ACK pulse of each byte. Accordingly, the following two should be considered as count start conditions. ➀ SDA falling edge caused by SCL/SDA interrupt This is the countermeasure for a communication interrupt in the middle of from START condition to a slave address. However, the detection condition must be considered because a interrupt is also generated by communication from other masters to other slaves. ➁ SMBUS interrupt after receiving slave address This is the countermeasure for when communication is interrupted from receiving a slave address until receiving a command. (2) Low hold of communication line The I2C-BUS interface conforms to the I2C-BUS Standard Specifications. However, because the use condition of SMBUS differs from the I2C-BUS’s, there is possibility of occurrence of the following problem. ➀ Low hold of SDA line caused by ACK pulse at voltage drop of communication line When the SMBUS voltage slowly drops, that is caused by extracting a battery from equipment or turning off a PC’s power or etc., it might be incorrectly treated as the SCL pulse near the threshold level voltage. When the SDA is judged “L” in that condition, it becomes the general call and the ACK is transmitted. However, when the SCL remains “L” at the ACK pulse, the SDA continuously remains “L” until input of the next SCL pulse. Countermeasure: As explained before, start the time out count at the falling of SDA line of START condition and reset ES0 bit of the S1D register when the time out is satisfied (Note). Note: Do not use the read-modify-write instruction at this time. Furthermore, when the ES0 bit is set to “0”, it becomes a general-purpose port ; so that the port must be set to input mode or “H”. |
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