M38041FFHKP datasheet(221/387 Pages) RENESAS

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2-97

APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

➀ After START condition, the masters, which have different speed, simultaneously start clock transmission.

➁ The SCL outputs “L” because (A) finished counting “H” output; then (B)’s “H” output counting is

interrupted and (B) starts counting “L” output.

➂ The (A) outputs “H” because (A) finished counting “L” term; the SCL level does not become “H”

because (B) outputs “L”, and counting “H” term does not start but stop.

➃ (B) outputs “L” term.

➄ The SCL outputs “H” because (B) finished counting “L” term; then (B)’s “H” output counting is

started at the same time as (A).

➅ The SCL outputs “L” because (A) first finished counting “H” output; then (B)’s “H” output counting

is interrupted and (B) starts counting “L” output.

➆ The above are repeatedly performed.

(2)

Clock synchronization during communication

In the I2C-BUS, the slave device is permitted to retain the SCL line “L” and become waiting status

for transmission from the master. By byte unit, for the reception preparation of the slave device, the

master can become waiting status by making the SCL line “L”, which is after completion of byte

reception or the ACK.

By bit unit, it is possible to slow down a clock speed by retaining the clock line “L” for slave devices

having limited hardware.

The 3804 group can transmit data correctly without reduction of data bits toward waiting status

request from the slave device. It is because the synchronization circuit is included for the case when

retaining the SCL line “L” as an internal hardware.

After the last bit, including the ACK bit, of a transmission/reception data byte, the SCL line automatically

remains “L” and waiting status is generated until completion of an interrupt process or reception

preparation.

(3)

Arbitration lost

A plural master exists on the same bus in the I2C-BUS and there are possibility to start communication

simultaneously. Even when the master devices having the same transmission frequency start

communication simultaneously, which device must transmit data correctly. Accordingly, there is the

definition to detect a communication confliction on the SDA line in the I2C-BUS.

The SDA line is output at the timing synchronized by the SCL, however, the synchronization among

the SDA signals is not performed.

Fig. 2.5.19 SCL waveforms when synchronizing clocks

SCL(A)

SCL(B)

SCL

➀

➁

➂

➃

➄

➅

➆

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