M38041FFHKP datasheet(134/387 Pages) RENESAS

134 / 387 page

2-10

APPLICATION

2.2 Interrupt

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Fig. 2.2.6 Structure of Interrupt control register 1

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

Interrupt control register 1

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt control register 1

(ICON1 : address 003E16)

Name

Functions

At reset R W

INT0/Timer Z

interrupt enable bit

INT1 interrupt

enable bit

Serial I/O1

transmit/SCL, SDA

interrupt enable bit

Timer X interrupt

enable bit

Timer Y interrupt

enable bit

Timer 1 interrupt

enable bit

Serial I/O1 receive

interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

Timer 2 interrupt

enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

Interrupt request register 2

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt request register 2

(IREQ2 : address 003D16)

Name

Functions

At reset R W

CNTR0/SCL, SDA

interrupt request bit

CNTR1/Serial I/O3

receive interrupt

request bit

INT2/I2C interrupt

request bit

INT3 interrupt

request bit

INT4/CNTR2

interrupt request bit

AD converter/Serial

I/O3 transmit

interrupt request bit

Serial I/O2/Timer Z

interrupt request bit

✽

Nothing is arranged for this bit. This is a write

disabled bit. When this bit is read out, the

contents are 0 .

✽: 0 can be set by software, but 1 cannot be set.