M38041FFHKP datasheet(380/387 Pages) RENESAS

380 / 387 page

Addressing mode

Symbol

Function

Details

IMP

IMM

BIT, A

BIT, ZP

OP n# OP n# OP n# OP n# OP n#

OP n

3-90

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.7 Machine instructions

When T = 0, this instruction subtracts the

value of M and the complement of C from A,

and stores the results in A and C.

When T = 1, the instruction subtracts the con-

tents of M and the complement of C from the

contents of M(X), and stores the results in

M(X) and C.

A remain unchanged, but status flag are

changed.

M(X) represents the contents of memory

where is indicated by X.

This instruction sets the designated bit i of A

or M.

This instruction sets C.

This instruction set D.

This instruction set I.

This instruction set T.

This instruction stores the contents of A in M.

The contents of A does not change.

This instruction resets the oscillation control F/

F and the oscillation stops. Reset or interrupt

input is needed to wake up from this mode.

This instruction stores the contents of X in M.

The contents of X does not change.

This instruction stores the contents of Y in M.

The contents of Y does not change.

This instruction stores the contents of A in X.

The contents of A does not change.

This instruction stores the contents of A in Y.

The contents of A does not change.

This instruction tests whether the contents of

M are “0” or not and modifies the N and Z.

This instruction transfers the contents of S in

This instruction stores the contents of X in A.

This instruction stores the contents of X in S.

This instruction stores the contents of Y in A.

The WIT instruction stops the internal clock

but not the oscillation of the oscillation circuit

is not stopped.

CPU starts its function after the Timer X over

flows (comes to the terminal count). All regis-

ters or internal memory contents except Timer

X will not change during this mode. (Of course

needs VDD).

SBC

(Note 1)

(Note 5)

SEB

SEC

SED

SEI

SET

STA

STP

STX

STY

TAX

TAY

TST

TSX

TXA

TXS

TYA

WIT

When T = 0

← A – M – C

When T = 1

M(X)

← M(X) – M – C

Ai or Mi

← 1

← A

← X

← Y

← A

M = 0?

← S

← X

← Y

Notes 1 : The number of cycles “n” is increased by 3 when T is 1.

2 : The number of cycles “n” is increased by 2 when T is 1.

3 : The number of cycles “n” is increased by 1 when T is 1.

4 : The number of cycles “n” is increased by 2 when branching has occurred.

5 : N, V, and Z flags are invalid in decimal operation mode.

E9 2

20i

E5 3

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