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M38044F2HKP датащи(PDF) 234 Page - Renesas Technology Corp |
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M38044F2HKP датащи(HTML) 234 Page - Renesas Technology Corp |
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234 / 387 page ![]() 2-110 APPLICATION 2.5 Multi-master I2C-BUS interface Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 3804 Group (Spec.H) ➂ Reception of RESTART condition and slave address After receiving a slave address, prepare transmission data. Judgment whether receiving data or transmitting is required, because the mode is automatically switched between the receive mode and the transmit mode depending on the R/W bit of the received slave address. Accordingly, judge whether read or write referring the slave address comparison flag (AAS bit; bit 2 of address 001316). Fig. 2.5.31 Reception process of RESTART condition and slave address 1 (transmitted) End S0 (address 001116) ← lower data Error end AAS (address 001316), bit 2 ? 1 (STOP condition) 1 (corresponded) S1 (address 001316) ← 000100002 TRX (address 001316), bit 6 ? 0 (not corresponded) End Slave receive processing, etc. • Judgment of bus hold • Judgment of transmit/receive mode • Slave receive mode set • Output lower data write to I2C data shift register PIN (address 001316), bit 4 ? 0 (lower data received) 3 0 (received) |
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