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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M38040F2HKP датащи(PDF) 366 Page - Renesas Technology Corp |
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M38040F2HKP датащи(HTML) 366 Page - Renesas Technology Corp |
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366 / 387 page  3-76 REJ09B0212-0100Z Rev.1.00 Jan 14, 2005 3804 Group (Spec.H) APPENDIX 3.5 Control registers Fig. 3.5.43 Structure of Flash memory control register 0 8 KB user block E/W enable bit (Notes 1, 2) Flash memory control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register 0 (FMCR0 : address 0FE016) b 0 1 2 4 Name Functions At reset R W 0 0 0 Not used (Do not write “1” to this bit.) CPU rewrite mode select bit (Note 1) 0 : Busy (being automatic written or automatic erased) 1 : Ready 0 0 0 0 RY/BY status flag Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: This bit can be written only when the CPU rewrite mode select bit is “1”. 3: Effective only when the CPU rewrite mode select bit = “1”. Fix this bit to “0” when the CPU rewrite mode select bit is “0”. 4: When setting this bit to “1” (when the control circuit of flash memory is reset), the flash memory cannot be accessed for 10 µs. 5: Write to this bit from program on RAM. 3 0: User ROM area is accessed 1: Boot ROM area is accessed Flash memory reset bit (Note 3) 0: Normal operation 1: Reset 0: E/W disabled 1: E/W enabled 0 : CPU rewrite mode invalid (software commandes invalid) 1 : CPU rewrite mode valid (Software commands acceptable) 1 User ROM area select bit 5 0: Pass 1: Error Program status flag 6 0: Pass 1: Error Erase status flag 7 |
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