SH7708 datasheet(227/633 Pages) RENESAS

номер детали	SH7708

подробное описание детали	SuperH??RISC engine

PDF	633 Pages

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производитель	RENESAS [Renesas Technology Corp]

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209

• For Normal Memory

Description

Bit 4: A1-2W0

Bit 3: A1-2W0

Inserted Wait States

WAIT Pin

Ignored

Enabled

Enabled (Initial value)

• For DRAM, Synchronous DRAM

Description

Bit 4: A1-2W0

Bit 3: A1-2W0

DRAM:

CAS Assert Period

SDRAM: CAS Latency

(Initial value)

Bits 2 to 0—Area 0 Wait Control (A0W2, A0W1, A0W0): These bits specify the number of wait

states inserted in physical space area 0. They also specify the burst pitch for burst transfer.

Description

First Cycle

Burst Cycle

(Excluding First Cycle)

Bit 2:

A0W2

Bit 1:

A0W1

Bit 0:

A0W0

Inserted

Wait States

WAIT Pin

Number of States

Per Data Transfer

WAIT Pin

Ignored

Enabled

10 (Initial value) Enabled

Enabled

10.2.5

Individual Memory Control Register (MCR)

The individual memory control register (MCR) is a 16-bit read/write register that specifies

RAS

and

CAS timing and burst control for DRAM (area 3 only), synchronous DRAM (areas 2 and 3),

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