SH7052 datasheet(116/919 Pages) RENESAS

номер детали	SH7052

подробное описание детали	SuperHTM RISC engine

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производитель	RENESAS [Renesas Technology Corp]

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• Bit 8—NMI Edge Select (NMIE)

Bit 8: NMIE

Description

Interrupt request is detected on falling edge of NMI input (Initial value)

Interrupt request is detected on rising edge of NMI input

• Bits 7 to 4—IRQ0 to IRQ3 Sense Select (IRQ0S to IRQ3S): These bits set the IRQ0 to IRQ3

interrupt request detection mode.

Bits 7 to 4:

IRQ0S to IRQ3S

Description

Interrupt request is detected on low level of IRQ input

(Initial value)

Interrupt request is detected on falling edge of IRQ input

• Bits 3 to 0—Reserved: These bits always read 0. The write value should always be 0.

6.3.3

IRQ Status Register (ISR)

ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins

IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be

withdrawn by writing 0 to IRQnF after reading IRQnF = 1.

A reset and hardware standby mode initialize ISR but software standby mode does not.

Bit:

——

———

—

Initial value:

R/W:

Bit:

IRQ0F

IRQ1F

IRQ2F

IRQ3F

—

Initial value:

R/W:

R/W

• Bits 15 to 8—Reserved: These bits always read 0. The write value should always be 0.

SH7052 датащи(PDF) 116 Page - Renesas Technology Corp