M32CSLASH86 datasheet(245/505 Pages) RENESAS

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Page 222

17. Serial I/O (Special Function)

)

(

17.5 Special Mode 3 (GCI Mode)

In GCI mode, the external clock is synchronized with the transfer clock used in the clock synchronous serial

I/O mode.

Table 17.24 lists specifications of GCI mode. Table 17.25 lists registers settings. Tables 17.26 to 17.28 list

pin settings.

Table17.24 GCI Mode Specifications

Item

Specification

Transfer Data Format

Transfer data : 8 bits long

Transfer Clock

The CKDIR bit in the UiMR register (i=0 to 4) is set to "1" (external clock selected):

input from the CLKi pin

________

Clock Synchronization Function Trigger signal input from the CTSi pin

Transmit/Receive Start

To start data transmission and reception, meet the following conditions and then apply a

Condition

________

trigger signal to the CTSi pin:

- Set the TE bit in the UiC1 register to "1" (transmit enable)

- Set the RE bit in the UiC1 register to "1" (receive enable)

- Set the TI bit in the UiC1 register to "0" (Data in the UiTB register)

Interrupt Request

• While transmitting, the following condition can be selected:

Generation Timing

- The UiIRS bit in the UiC1 register is set to "0" (UiTB register empty):

when data is transferred from the UiTB register to the UARTi transmit register (transmission started)

- The UiIRS bit is set to "1" (Transmit completed):

when a data transmission from the UARTi transfer register is completed

• While receiving,

when data is transferred from the UARTi receive register to the UiRB register (reception

completed)

Error Detection

Overrun error(1)

This error occurs when the seventh bit of the next received data is read before reading the

UiRB register.

NOTES:

1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to

"1" (interrupt requested).

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