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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M32C/86 датащи(PDF) 221 Page - Renesas Technology Corp |
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M32C/86 датащи(HTML) 221 Page - Renesas Technology Corp |
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221 / 505 page  Page 198 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 17. Serial I/O (Clock Synchronous Serial I/O) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M D0 D1 D2 D3 D4 D5 D6 D7 TxDi (no inverse) Transfer clock "H" "L" "H" "L" TxDi (inverse) "H" "L" (1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (not inversed) Transfer clock "H" "L" (2) When the UiLCH bit in the UiC1 register is set to "1" (inverse) NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge) and the UFORM bit in the UiC0 register is set to "0" (LSB first). D0 D1 D2 D3 D4 D5 D6 D7 17.1.3 Continuous Receive Mode When the UiRRM bit in the UiC1 register (i=0 to 4) is set to "1" (continuous receive mode), the TI bit is set to "0" (data in the UiTB register) by reading the UiRB register. When the UiRRM bit is set to "1", do not set dummy data in the UiTB register by program. 17.1.4 Serial Data Logic Inverse When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB register. Figure 17.13 shows a switching example of the serial data logic. Figure 17.13 Serial Data Logic Inverse |
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