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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M32C/86 датащи(PDF) 156 Page - Renesas Technology Corp |
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M32C/86 датащи(HTML) 156 Page - Renesas Technology Corp |
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156 / 505 page  Page 133 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 13. DMAC ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M (1) When 8-bit data is transferred or when 16-bit data is transferred with a 16-bit data bus from an even source address CPU Clock Address Bus RD Signal WR Signal Data Bus (3) When one wait state is inserted into the source-read bus cycle under the conditions in (1) (2) When 16-bit data is transferred from an odd source address or when 16-bit data is transferred and 8-bit bus is used to access a source address CPU Clock Address Bus RD Signal WR Signal Data Bus CPU Use CPU Use CPU Use CPU Use Source Source Source + 1 Source + 1 (4) When one wait state is inserted into the source-read bus cycle under the conditions in (2) NOTES: 1. The above applies when the destination-write bus cycle is 2 CPU clock cycles (=1 bus cycle). However, if the destination-write bus cycle is pleaced under these conditions, it will change to the same timing as the source-read cycle illustrated above. Destination Destination CPU Clock Address Bus RD Signal WR Signal Data bus CPU Use CPU Use CPU Use CPU Use Source Source Destination Destination CPU Clock Address Bus RD Signal WR Signal Data Bus CPU Use CPU Use CPU Use CPU Use Source Source Source + 1 Source + 1 Destination Destination CPU Use CPU Use Source Destination CPU Use CPU Use Source Destination CPU Clock Figure 13.6 Transfer Cycle Examples with the Source-Read Bus Cycle |
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