M32CSLASH86 datasheet(126/505 Pages) RENESAS

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Page 103

11. Interrupts

)

(

Table 11.2 Relocatable Vector Tables (Continued)

Interrupt Generated by

Vector Table Address

Software

Reference

Address(L) to Address(H)(1)

Interrupt Number

Bus Conflict Detect, Start Condition Detect, +156 to +159 (009C16 to 009F16) 39

Serial I/O

Stop Condition Detect (UART2)(3),

Bus Conflict Detect, Start Condition Detect, +160 to +163 (00A016 to 00A316)40

Stop Condition Detect (UART3/UART0)(4)

Bus Conflict Detect, Start Condition Detect, +164 to +167 (00A416 to 00A716)41

Stop Condition Detect (UART4/UART1)(4)

A/D0

+168 to +171 (00A816 to 00AB16) 42

A/D Converter

Key Input

+172 to +175 (00AC16 to 00AF16) 43

Interrupts

Intelligent I/O Interrupt 0, CAN 3

+176 to +179 (00B016 to 00B316) 44

Intelligent I/O

Intelligent I/O Interrupt 1, CAN 4

+180 to +183 (00B416 to 00B716) 45

CAN

Intelligent I/O Interrupt 2

+184 to +187 (00B816 to 00BB16)46

Intelligent I/O Interrupt 3

+188 to +191 (00BC16 to 00BF16)47

Intelligent I/O Interrupt 4

+192 to +195 (00C016 to 00C316)48

CAN 5

+196 to +199 (00C416 to 00C716) 49

CAN

Reserved Space

+200 to +207 (00C816 to 00CF16) 50, 51

Intelligent I/O Interrupt 8

+208 to +211 (00D016 to 00D316) 52

Intelligent I/O

Intelligent I/O Interrupt 9, CAN 0

+212 to +215 (00D416 to 00D716) 53

CAN

Intelligent I/O Interrupt 10, CAN 1

+216 to +219 (00D816 to 00DB16)54

Reserved Space

+220 to +227 (00DC16 to 00E316) 55, 56

CAN 2

+228 to +231 (00E416 to 00E716) 57

CAN

Reserved Space

+232 to +255 (00E816 to 00FF16) 58 to 63

INT Instruction(2)

+0 to +3 (000016 to 000316) to

0 to 63

Interrupts

+252 to +255 (00FC16 to 00FF16)

NOTES:

1. These addresses are relative to those in the INTB register.

2. The I flag does not disable interrupts.

3. In I2C mode, NACK, ACK or start/stop condition detection causes interrupts to be generated.

4. The IFSR6 bit in the IFSR register determines whether these addresses are used for an interrupt in UART0 or in

UART3.

The IFSR7 bit in the IFSR register determines whether these addresses are used for an interrupt in UART1 or in

UART4.

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