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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M32C/86 датащи(PDF) 107 Page - Renesas Technology Corp |
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M32C/86 датащи(HTML) 107 Page - Renesas Technology Corp |
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107 / 505 page  Page 84 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 9. Clock Generation Circuit ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Figure 9.12 Procedure to Use PLL Clock as CPU Clock Source Use PLL clock as CPU clock source Set the PLC0 and the PLC1 registers (Set the PLC07 bit to "0") Set the CM17 bit to "1" (PLL clock as CPU clock source) PLC07 bit : Bit in the PLC0 Register CM17 bit : Bit in the CM1 Register Set the PLC07 bit to "1" (PLL on) Wait tsu(PLL)ms End 9.1.4 PLL Clock The PLL frequency synthesizer generates the PLL clock based on the main clock. The PLL clock can be used as clock source for the CPU clock and peripheral function clock. The PLL frequency synthesizer stops after reset. When the PLC07 bit is set to "1" (PLL on), the PLL frequency synthesizer starts operating. Wait tsu(PLL) ms for the PLL clock to stabilize. The PLL clock can either be the clock output from the voltage controlled oscillator (VCO) divided-by-2 or divided-by-3. When the PLL clock is used as a clock source for the CPU clock or peripheral function clock, set each bit as is shown in Table 9.3. Figure 9.12 shows the procedure to use the PLL clock as the CPU clock source. To enter wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source), set the PLC07 bit in the PLC0 register to "0" (PLL off) and then enter wait or stop mode. Table 9.3 Bit Settings to Use PLL Clock as CPU Clock Source X ( f N I ) r e t s i g e R 0 C L Pr e t s i g e R 1 C L P k c o l C L L P t i B 2 0 C L Pt i B 1 0 C L Pt i B 0 0 C L Pt i B 1 2 M C z H M 0 10 1 1 0z H M 0 3 1z H M 0 2 z H M 81 0 0 0z H M 2 3 1z H M 3 . 1 2 |
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