H8SXSLASH1663M datasheet(609/1504 Pages) RENESAS

номер детали	H8SX/1663M

подробное описание детали	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

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Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 577 of 1468

REJ09B0412-0200

Clock

Address

DTC activation

request

DTC request

Clock

Address

DTC activation

request

DTC request

Clock

Address

DTC activation

request

DTC request

[Example 1: When an odd address and even address are specified in SAR and DAR, respectively, and when the data size of transfer is specified as word]

[Example 2: When an odd address and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword]

[Example 3: When address 4n + 2 and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword]

Vector read

Transfer information

read

Data transfer Transfer information

write

Vector read

Transfer information

read

Data transfer Transfer information

write

Vector read

Transfer information

read

Data transfer

Transfer information

write

Figure 12.5 Bus Cycle Division Example

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