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H8SX1663 датащи(PDF) 330 Page - Renesas Technology Corp

номер детали H8SX1663
подробное описание детали  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 278 of 1102
REJ09B0294-0100
When the time between the REF command and the subsequent ACTV command does not meet a
given specification, a wait cycle can be inserted for one to seven cycles during a refresh cycle by
bits RLW2 to RLW0 in REFCR. Set the bit according to the SDRAM to be used and the
frequency of this LSI so that the number of wait cycles can be optimal.
Figure 6.78 shows a timing example when the one wait cycle is inserted.
TR
p
TR
r
TR
cw
TR
c1
TR
c2
Address bus
SD
φ
CS
Precharge-sel
RAS
CAS
WE
CKE
PALL
REF
NOP
BS
RD/
WR
High
High
High
Figure 6.78 Auto-Refresh Timing (TPC1 = 0, TPC0 = 0, RLW2 = 0, RLW1 = 0, RLW0 = 1)



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