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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H8SX1663 датащи(PDF) 221 Page - Renesas Technology Corp |
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H8SX1663 датащи(HTML) 221 Page - Renesas Technology Corp |
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221 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 169 of 1102 REJ09B0294-0100 6.4 Multi-Clock Function and Number of Access Cycles The internal functions of this LSI operate synchronously with the system clock (I φ), the peripheral module clock (P φ), or the external bus clock (Bφ). Table 6.1 shows the synchronization clock and their corresponding functions. Table 6.1 Synchronization Clocks and Their Corresponding Functions Synchronization Clock Function Name I φ MCU operating mode Interrupt controller Bus controller CPU DTC DMAC Internal memory Clock pulse generator Power down control P φ I/O ports TPU PPG TMR WDT SCI A/D D/A IIC2 USB B φ External bus interface The frequency of each synchronization clock (I φ, Pφ, and Bφ) is specified by the system clock control register (SCKCR) independently. For further details, see section 22, Clock Pulse Generator. There will be cases when P φ and Bφ are equal to Iφ and when Pφ and Bφ are different from Iφ according to the SCKCR specifications. In any case, access cycles for internal peripheral functions and external space is performed synchronously with P φ and Bφ, respectively. |
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