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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H8SX1663 датащи(PDF) 216 Page - Renesas Technology Corp |
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H8SX1663 датащи(HTML) 216 Page - Renesas Technology Corp |
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216 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 164 of 1102 REJ09B0294-0100 Bit Bit Name Initial Value R/W Description 15 CMF 0 R/(W)* Compare Match Flag Indicates that the refresh timer counter (RTCNT) and refresh timer constant register (RTCOR) match. [Clearing conditions] • When 0 is written to this bit after this bit is read as 1 with RFSHE = 0 • When CBR refresh is performed with RFSHE = 1 [Setting condition] • When RTCNT matches RTCOR 14 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables an interrupt request (CMIF) when the CMF flag is set to 1. This bit is effective when refresh control is not performed (RFSHE = 0). When refresh control is performed (RFSHE = 1), this bit is always cleared to 0. This bit cannot be modified. 13 to 12 RCW1 RCW0 0 0 R/W R/W CAS-RAS Wait Control Select the number of wait cycles inserted between the CAS asserted cycle and CAS asserted cycle during DRAM refresh. When the SDRAM space is selected, these bits do not affect operations although they can be read from or written to. 00: No wait cycle inserted 01: One wait cycle inserted 10: Two wait cycles inserted 11: Three wait cycles inserted 11 0 R Reserved The initial value should not be changed. |
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