H8SX1663 datasheet(154/1158 Pages) RENESAS

номер детали	H8SX1663

подробное описание детали	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 102 of 1102

REJ09B0294-0100

5.3.5

IRQ Sense Control Registers H and L (ISCRH, ISCRL)

ISCRH and ISCRL select the source that generates an interrupt request from IRQ15, and IRQ11 to

IRQ0 input.

Upon changing the setting of ISCR, IRQnF (n = 0 to 11, and 15) in ISR is often set to 1

accidentally through an internal operation. In this case, an interrupt exception handling is executed

if an IRQn interrupt request is enabled. In order to prevent such an accidental interrupt from

occurring, the setting of ISCR should be changed while the IRQn interrupt is disabled, and then

the IRQnF in ISR should be cleared to 0.

• ISCRH

Bit

Bit Name

Initial Value

R/W

Bit

Bit Name

Initial Value

R/W

IRQ15SR

R/W

IRQ15SF

R/W



R/W



R/W



R/W



R/W



R/W



R/W

IRQ11SR

R/W

IRQ11SF

R/W

IRQ10SR

R/W

IRQ10SF

R/W

IRQ9SR

R/W

IRQ9SF

R/W

IRQ8SR

R/W

IRQ8SF

R/W

• ISCRL

Bit

Bit Name

Initial Value

R/W

Bit

Bit Name

Initial Value

R/W

IRQ7SR

R/W

IRQ7SF

R/W

IRQ6SR

R/W

IRQ6SF

R/W

IRQ5SR

R/W

IRQ5SF

R/W

IRQ4SR

R/W

IRQ4SF

R/W

IRQ3SR

R/W

IRQ3SF

R/W

IRQ2SR

R/W

IRQ2SF

R/W

IRQ1SR

R/W

IRQ1SF

R/W

IRQ0SR

R/W

IRQ0SF

R/W

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