H8SX1663 datasheet(141/1158 Pages) RENESAS

номер детали	H8SX1663

подробное описание детали	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 4 Exception Handling

Rev.1.00 Jun. 07, 2006 Page 89 of 1102

REJ09B0294-0100

Table 4.9

Status of CCR and EXR after Sleep Instruction Exception Handling

CCR

EXR

Interrupt Control Mode

I2 to I0



[Legend]

Set to 1

Cleared to 0

:

Retains the previous value.

4.7.3

Exception Handling by Illegal Instruction

The illegal instructions are general illegal instructions and slot illegal instructions. The exception

handling by the general illegal instruction starts when an undefined code is executed. The

exception handling by the slot illegal instruction starts when a particular instruction (e.g. its code

length is two words or more, or it changes the PC contents) at a delay slot (immediately after a

delayed branch instruction) is executed. The exception handling by the general illegal instruction

and slot illegal instruction is always executable in the program execution state.

The exception handling is as follows:

1. The contents of PC, CCR, and EXR are saved in the stack.

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. An exception handling vector table address corresponding to the occurred exception is

generated, the start address of the exception service routine is loaded from the vector table to

PC, and program execution starts from that address.

Table 4.10 shows the state of CCR and EXR after execution of illegal instruction exception

handling.

H8SX1663 датащи(PDF) 141 Page - Renesas Technology Corp