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H8SX1663 датащи(PDF) 894 Page - Renesas Technology Corp

номер детали H8SX1663
подробное описание детали  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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Section 17 I
2C Bus Interface 2 (IIC2)
Rev.1.00 Jun. 07, 2006 Page 842 of 1102
REJ09B0294-0100
ICDRS
ICDRR
A
A
RDRF
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
12
34
56
78
9
SCL
(Master output)
Data 2
Data 1
Data 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
User
processing
[3] Set ACKBT
[3] Read ICDRR
[4] Read ICDRR
Figure 17.12 Slave Receive Mode Operation Timing 2
17.4.6
Noise Canceler
The logic levels at the SCL and SDA pins are routed through the noise cancelers before being
latched internally. Figure 17.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The signal input to SCL
(or SDA) is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
C
Q
D
C
Q
D
Sampling clock
Sampling
clock
SCL input
or
SDA input
Latch
System clock period
Latch
Compare
match
detection
circuit
Internal SCL
or
internal SDA
Sampling clock
Figure 17.13 Block Diagram of Noise Canceler



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