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H8SX1663 датащи(PDF) 402 Page - Renesas Technology Corp

номер детали H8SX1663
подробное описание детали  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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Section 7 DMA Controller (DMAC)
Rev.1.00 Jun. 07, 2006 Page 350 of 1102
REJ09B0294-0100
Figure 7.10 shows an example of the DMA transfer timing in block transfer mode. The transfer
conditions are as follows:
• Address mode: single address mode
• Data access size: byte
• 1-block size: three bytes
The block transfer mode operations in single address mode and in dual address mode are shown in
figures 7.11 and 7.12, respectively.
CPU
CPU
DMAC
DMAC
DMAC
CPU
Bus cycle
TEND
DREQ
No CPU cycle generated
Transfer cycles for one block
Figure 7.10 Operations in Block Transfer Mode
Transfer
Address T
Address B
DACK
Block
BKSZH
×
data access size
Figure 7.11 Operation in Single Address Mode in Block Transfer Mode
(Block Area Specified)



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