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HD64F2149YV датащи(PDF) 126 Page - Renesas Technology Corp

номер детали HD64F2149YV
подробное описание детали  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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HD64F2149YV датащи(HTML) 126 Page - Renesas Technology Corp

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Section 4 Exception Handling
Rev. 3.00 Jan 18, 2006 page 98 of 1044
REJ09B0280-0300
4.4
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.3 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.3
Status of CCR and EXR after Trap Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
I2 to I0
T
01
—
—
—
11
1
—
—
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.



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