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M32C/8B датащи(PDF) 250 Page - Renesas Technology Corp |
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M32C/8B датащи(HTML) 250 Page - Renesas Technology Corp |
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250 / 406 page ![]() SCLi SDAi i = 0 to 4 (1) In slave mode, the CKDIR bit is set to 1 (external clock) and the STSPSEL bit is set to 0 (no start condition and stop condition output) (2) In master mode, the CKDIR bit is set to 0 (internal clock) and the STSPSEL bit is set to 1 (start condition and stop condition output) Start condition detection interrupt SCLi SDAi Start condition detection interrupt Stop condition detection interrupt 01 0 0 1 Setting value of STSPSEL bit The STAREQ bit is set to 1 (start) The STAREQ bit is set to 1 (start) Stop condition detection interrupt 1 0 IR bit in the BCNiIC register Set to 0 by an interrupt request acknowledgement or by a program 1 0 IR bit in the BCNiIC register Set to 0 by an interrupt request acknowledgement or by a program Under development M32C/8B Group 17. Serial Interfaces Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 233 of 385 Figure 17.26 STSPSEL Bit Function |
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