M32CSLASH8B datasheet(239/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 222 of 385

17.1.2.3 Serial Data Logic Inverse

When the UiLCH bit in the UiC1 register is set to 1 (inverted), data logic written in the UiTB register is inverted

for transmit operation. A read from the UiRB register returns the inverted logic of receive data. This function

can be used when data length is 7 bits or 8 bits long. Figure 17.21 shows an example of serial data logic inverse

operation.

Figure 17.21

Serial Data Logic Inverse

17.1.2.4 TXD and RXD I/O Polarity Inverse

The level output from the TXD pin and the level applied to the RXD pin are inverted with this function. When

the IOPOL bit in the UiMR register (i = 0 to 4) is set to 1 (inverted), all the input/output data levels, including

the start bit, stop bit and parity bit, are inverted. Figure 17.22 shows TXD and RXD I/O polarity inverse.

Figure 17.22

TXD and RXD I/O Polarity Inverse

(1) When the UiLCH bit in the UiC1 register (i = 0 to 4) is set to 0 (not inverted)

(2) When the UiLCH bit is set to 1 (inverted)

TXDi

(not inverted)

The above applies under the following conditions:

- UiC0 register: UFORM bit = 0 (LSB first)

- UiMR register: STPS bit = 0 (1 stop bit)

PRYE bit = 1 (parity enabled).

"H"

"L"

"H"

"L"

TXDi

(inverted)

(1) When the IOPOL bit in the UiMR register (i = 0 to 4) is set to 0 (not inverted)

(2) When the IOPOL bit is set to 1 (inverted)

TXDi

(not inverted)

The above applies under the following conditions:

- UiC0 register: UFORM bit = 0 (LSB first)

- UiMR register: STPS bit = 0 (1 stop bit)

PRYE bit = 1 (parity enabled)

"H"

"L"

RXDi

(not inverted)

"H"

"L"

TXDi

(inverted)

"H"

"L"

RXDi

(inverted)

"H"

"L"

ST: Start bit

P: Parity bit

SP: Stop bit

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