M32CSLASH8B datasheet(219/406 Pages) RENESAS

219 / 406 page

Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 202 of 385

Figure 17.6

U0SMR4 to U4SMR4 Registers

b7 b6 b5 b4

Symbol

U0SMR4 to U2SMR4

U3SMR4, U4SMR4

Address

0364h, 02E4h, 0334h

0324h, 02F4h

After Reset

00h

Function

Bit Symbol

Bit Name

STPREQ

RSTAREQ

STAREQ

ACKC

SCLHI

0: Serial input/output circuit selected

1: Start/stop condition generation circuit

selected(4)

SCL, SDA output select bit(1, 5)

Start condition generate bit(1, 3)

ACKD

STSPSEL

0: ACK

1: NACK

ACK data bit(2, 5)

0: Serial data output

1: ACK data output

ACK data output enable bit(2, 5)

SWC9

UARTi Special Mode Register 4 (i = 0 to 4)

Restart condition generate

bit(1, 3)

Stop condition generate bit(1, 3)

0: Clear

1: Start

0: Clear

1: Start

0: Clear

1: Start

NOTES:

1. These bits are used when the MCU is in master mode in I 2C mode.

2. These bits are used when the MCU is in slave mode in I 2C mode.

3. When each condition generation is completed, the corresponding bit becomes 0. When a condition generation is failed, the bit

remains 1.

4. Set the STSPSEL bit to 1 (start/stop condition generation circuit selected) after setting the STAREQ bit, RSTAREQ bit, or

STPREQ bit to 1 (start).

5. Bits STPSEL, ACKD, ACKC, SCLHI, and SWC9 can be set to 1 when the IICM bit in the UiSMR register is set to 1 (I 2C mode).

When the IICM bit is set to 0 (Other than I 2C mode), these bits become 0.

SCL wait output bit 3(1, 5)

SCL output stop bit(1, 5)

0: No wait state/release wait state

1: SCLi pin is held "L" after receiving 9th bit

When the bus is free,

0: SCLi output not stopped

1: SCLi output stopped

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