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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M32C/8B датащи(PDF) 214 Page - Renesas Technology Corp |
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M32C/8B датащи(HTML) 214 Page - Renesas Technology Corp |
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214 / 406 page  Under development M32C/8B Group 17. Serial Interfaces Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 197 of 385 17.1 UART0 to UART4 Figure 17.1 shows a UART0 to UART4 block diagram. Figures 17.2 to 17.10 show the registers associated with UART0 to UART4. Refer to the tables listing for register and pin settings in each mode. Figure 17.1 UART0 to UART 4 Block Diagram m = Setting value of the UiBRG register NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Select either Input/output port (CLKi input) or CLKi output in the Function Select Registers. (Refer to the chapter Programmable I/O Ports .) 3. Select either Input/output port or RTSi output in the Function Select Registers. (Refer to the chapter Programmable I/O Ports.) Logic inverse circuit + MSB/LSB conversion circuit High-order bits of data bus Low-order bits of data bus i = 0 to 4 SP: Stop bit PAR: Parity bit SMD2 to SMD0, STPS, PRYE, IOPOL, and CKDIR: bits in the UiMR register CLK1 and CLK0, CKPOL, CRD, and CRS: bits in the UiC0 register UiERE: bit in the UiC1 register UARTi transmit shift register Logic inverse circuit + MSB/LSB conversion circuit D0 D1 D2 D3 D4 D5 D6 D7 UiTB register b0 b1 b2 b3 b4 b5 b6 D8 PRYE 0 PAR STPS 0 SP SP TXDi UiERE 0 1 Error signal output circuit D8 0 0 0 0 0 0 0 D0 D1 D2 D3 D4 D5 D6 D7 UiRB register 1 1 IOPOL 0 1 RXDi IOPOL 0 UARTi receive shift register SMD2 to SMD0 b0 b1 b2 b3 b4 b5 b6 b7 100 001 101 110 b8 110 001 101 PRYE 0 PAR STPS 0 SP SP 001 100 101 110 1 1 1 SMD2 to SMD0 b7 100 001 101 110 b8 110 001 101 001 100 101 110 TXDi CKPOL CTSi / RTSi 100, 101, 110 SMD2 to SMD0 00 01 10 f1 f8 F2n(1) CLK1 and CLK0 RXDi RTSi output CTSi input Function Select Register(3) CKDIR UiBRG register 001 Receive clock Transmit clock 100, 101, 110 001 Receive control circuit Transmit control circuit Transmit/ receive unit 1/(m+1) 1/16 1/16 1/2 Polarity switching CRD CRS 0 1 CKDIR 0 1 CLKi Polarity switching Function Select Register(2) CLKi output CLKi input |
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