M32CSLASH8B datasheet(202/406 Pages) RENESAS

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Under development

M32C/8B Group

16. Three-Phase Motor Control Timer Function

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 185 of 385

Figure 16.7

TB2SC Register, ICTB2 Register

Bit Name

b6 b5 b4

Symbol

TB2SC

Address

035Eh

After Reset

00h

Function

Bit Symbol

Timer B2 Special Mode Register

PWCON

Timer B2

reload timing switch bit

0: Timer B2 underflow

1: Timer B2 underflow at the rising edge of the

timer A1 reload control signal

(every odd-numbered timer B2 underflow)

−

(b7-b1)

Reserved bits

Set to 0

Timer B2 Interrupt Generation Frequency Set Counter(1, 2)

Symbol

ICTB2

Address

030Dh

After Reset

Undefined

NOTES:

1. Read-modify-write instructions cannot be used to set the ICTB2 register. Refer to Usage Notes for details.

2. If the INV01 bit in the INVC0 register is set to 1, set the ICTB2 register while the TB2S bit is set to 0 (count stops). If the INV01

bit is set to 0, do not set the ICTB2 register when timer B2 underflows, regardless of the TB2S bit setting.

−

Function

Unimplemented.

Write 0. Read as undefined value.

Setting Range

b6 b5 b4 b3

1 to 15

- When the INV01 bit in the INVC0 register is set to 0 (the ICTB2

counter increments every timer B2 underflows) and a setting

value is n, the timer B2 interrupt request is generated every n-th

timer B2 underflow.

- When bits INV01 and INV00 are set to 10b (the ICTB2 counter

increments when the timer B2 underflow at the rising edge of the

timer A1 reload control signal) and a setting value is n, the first

timer B2 interrupt request is generated at the (2n-1)th timer B2

underflow. From the 2nd time on, the request is generated every

2n-th timer B2 underflow.

- When bits INV01 and INV00 are set to 11b (the ICTB2 counter

increments when the timer B2 underflow occurs at the falling edge

of the timer A1 reload control signal) and a setting value is n;

• When n

> 1, the first timer B2 interrupt request is generated at

the (2n-2)th timer B2 underflow. From the 2nd time on, the

request is generated every 2n-th timer B2 underflow.

• When n = 1, the timer B2 interrupt request is generated every

2n-th timer B2 underflow.

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