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M32C/8B датащи(PDF) 143 Page - Renesas Technology Corp |
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M32C/8B датащи(HTML) 143 Page - Renesas Technology Corp |
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143 / 406 page ![]() Under development M32C/8B Group 13. DMAC Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 126 of 385 Figure 13.5 DMD0 Register b7 b6 b5 b4 b1 b2 b3 DMA Mode Register 0(1) Symbol DMD0 Address (CPU internal register) Bit Symbol RW MD00 After Reset 00h RW NOTE: 1. Use the LDC instruction to set the DMD0 register. b0 MD01 RW RW BW0 RW0 MD10 RW1 RW RW MD11 BW1 RW RW RW Channel 0 transfer unit select bit Channel 1 transfer unit select bit Channel 0 transfer mode select bits Channel 0 transfer direction select bit Channel 1 transfer mode select bits Channel 1 transfer direction select bit Bit Name Function 0: 8 bits 1: 16 bits 0: 8 bits 1: 16 bits b1 b0 0 0: DMA disabled 0 1: Single transfer 1 0: Do not set to this value 1 1: Repeat transfer 0: Fixed address to incremented address 1: Incremented address to fixed address b5 b4 0 0: DMA disabled 0 1: Single transfer 1 0: Do not set to this value 1 1: Repeat transfer 0: Fixed address to incremented address 1: Incremented address to fixed address |
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