M32CSLASH8B datasheet(107/406 Pages) RENESAS

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Under development

M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 90 of 385

Table 9.8

Interrupts to Exit Wait Mode and Usage Conditions

9.5.3

Stop Mode

In stop mode, all clocks are stopped. Since the CPU clock and peripheral function clocks are stopped, the CPU

and the peripheral functions which are operated by these clocks stop their operation. The least power is required

to operate the MCU in stop mode. Enter stop mode from main clock mode.

9.5.3.1

Entering Stop Mode

Stop mode is entered by setting the CM10 bit in the CM1 register to 1 (all clocks stop) while the NMI pin is

held “H”. Also, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode) by setting the

CM10 bit to 1. To enter stop mode, the MRS bit in the VRCR register is set to 0 (main voltage regulator

operates).

Figure 9.18 shows a procedure to enter stop mode.

When entering stop mode, the instructions following CM10 = 1 instruction are stored into the instruction queue,

and the program stops. When stop mode is exited, the instruction lined in the queue is executed before the exit

interrupt routine is handled.

Insert the jmp.b instruction as follows after the instruction to set the CM10 bit to 1.

fset I

; I flag is set to 1

bset 0, cm1

; all clocks stopped (stop mode)

jmp.b LABEL_001

; jmp.b instruction executed (no instruction between jmp.b and LABEL.)

LABEL_001:

nop

; nop(1)

nop

; nop(2)

nop

; nop(3)

nop

; nop(4)

mov.b #0, prcr

; protection set

Interrupt

When CM02 = 0

When CM02 = 1

NMI interrupt

Available

Voltage monitor interrupt

Available

Serial interface interrupt

Available when the source clock is the

internal clock or external clock.

Available when the source clock is the

external clock or f2n (when fXIND or on-

chip oscillator clock is selected).

Key input interrupt

Available

A/D conversion interrupt

Available in one-shot mode or single-

sweep mode

Not available

Timer A interrupt

Timer B interrupt

Available in all modes

Available in event counter mode or when

the count source is fC32 or f2n (when

fXIND or on-chip oscillator clock is

selected)

INT interrupt

Available

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