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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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R8C2K датащи(PDF) 330 Page - Renesas Technology Corp |
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R8C2K датащи(HTML) 330 Page - Renesas Technology Corp |
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330 / 471 page  R8C/2K Group, R8C/2L Group 16. Timers Rev.1.10 Dec 21, 2007 Page 313 of 450 REJ09B0406-0110 • The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment operation. The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at underflow in the TRD1 register), the content in the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During FFFFh, 0, 1 operation, data are not transferred to registers such as the TRDGRB0 register. Also, at this time, the OVF bit remains unchanged. Figure 16.148 Operation when TRD1 Register Underflows in Complementary PWM Mode No change UDF bit in TRDSR0 register Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Count value in TRD0 register Set to 0 by a program Not transferred from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 10b (transfer from the buffer register to the general register when the TRD1 register underflows). OVF bit in TRDSR0 register FFFFh 1 0 1 0 0 1 |
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