R8C2K datasheet(302/471 Pages) RENESAS

302 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 285 of 450

REJ09B0406-0110

Figure 16.125 TRDFCR Register in Complementary PWM Mode

Timer RD Function Control Register

Symbol

Address

After Reset

TRDFCR

013Ah

10000000b

Bit Symbol

Bit Name

Function

NOTES:

Set the ADCAP bit in the ADC0N0 register to 1 (starts by timer RD).

When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the setting of

the TRDPMR register.

STCLK

External clock input select bit

0 : External clock input disabled

1 : External clock input enabled

PWM3

ADTRG

ADEG

A/D trigger edge select bit

(in complementary PWM mode)

0 : A/D trigger is generated at

compare match betw een registers

TRD0 and TRDGRA0

1 : A/D trigger is generated at underflow

in the TRD1 register

PWM3 mode select bit(4)

This bit is disabled in complementary PWM

mode.

Normal-phase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

0 : Initial output “H”

Active level “L”

1 : Initial output “L”

Active level “H”

Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).

OLS0

Counter-phase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

0 : Initial output “H”

Active level “L”

1 : Initial output “L”

Active level “H”

A/D trigger enable bit

(in complementary PWM mode)

0 : Disable A/D trigger

1 : Enable A/D trigger(3)

CMD1

Combination mode select bits(1,2)

b1 b0

1 0 : Complementary PWM mode

(transfer from the

buffer register to the general

the TRD1 register)

1 1 : Complementary PWM mode

(transfer from the

buffer register to the general

registers TRD0 and TRDGRA0.)

Other than above : Do not set.

CMD0

b7 b6 b5 b4

When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is

enabled.

b3 b2

OLS1

b1 b0

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