R8C2K datasheet(250/471 Pages) RENESAS

250 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 233 of 450

REJ09B0406-0110

Figure 16.74

Registers TRDCR0 to TRDCR1 in Input Capture Function

Timer RD Control Register i (i = 0 or 1)

Symbol

Address

After Reset

TRDCR0

TRDCR1

0140h

0150h

00h

Bit Symbol

Bit Name

Function

NOTES:

TCK1

TCK0

CCLR2

CCLR1

Count source select bits

b2 b1 b0

0 0 0 : f1

0 0 1 : f2

0 1 0 : f4

0 1 1 : f8

1 0 0 : f32

1 0 1 : TRDCLK input(1)

1 1 0 : fOCO40M

1 1 1 : Do not set.

External clock edge select bits(2) b4 b3

0 0 : Count at the rising edge

0 1 : Count at the falling edge

1 0 : Count at both edges

1 1 : Do not set.

b7 b6 b5 b4 b3 b2

CKEG0

b1 b0

TCK2

This setting is enabled w hen the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate

synchronously).

Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the

TRDFCR register is set to 1 (external clock input enabled).

CKEG1

CCLR0

b7 b6 b5

0 0 0 : Disable clear (free-running

operation)

0 0 1 : Clear by input capture in the

TRDGRAi register

0 1 0 : Clear by input capture in the

TRDGRBi register

0 1 1 : Synchronous clear (clear

simultaneously w ith other

channel counter)(3)

1 0 0 : Do not set.

1 0 1 : Clear by input capture in the

TRDGRCi register

1 1 0 : Clear by input capture in the

TRDGRDi register

1 1 1 : Do not set.

TRDi counter clear select bits

This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).

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