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R8C2K датащи(PDF) 167 Page - Renesas Technology Corp

номер детали R8C2K
подробное описание детали  RENESAS MCU R8C FAMILY / R8C/2x SERIES
PDF  471 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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R8C2K датащи(HTML) 167 Page - Renesas Technology Corp

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R8C/2K Group, R8C/2L Group
16. Timers
Rev.1.10
Dec 21, 2007
Page 150 of 450
REJ09B0406-0110
Figure 16.11
Operating Example of Pulse Period Measurement Mode
Underflow signal of
timer RA prescaler
NOTES:
1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode.
2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer
RA prescaler underflows for the second time.
3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found).
The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge
is input, the measured result of the previous period is retained.
4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the
TUNDF bit in the TRACR register.
5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit.
6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously.
0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh
01h 00h 0Fh 0Eh
0Fh
0Dh
0Fh
0Bh 0Ah
0Dh
01h 00h 0Fh 0Eh
09h
TSTART bit in
TRACR register
1
0
1
0
1
0
TEDGF bit in
TRACR register
1
0
Measurement pulse
(TRAIO pin input)
Contents of TRA
1
0
Contents of read-out
buffer(1)
IR bit in TRAIC
register
TUNDF bit in
TRACR register
Set to 1 by program
Starts counting
TRA reloads
TRA read(3)
Retained
Set to 0 by program
Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with
the default value of the TRA register as 0Fh.
0Eh
TRA reloads
Retained
Set to 0 when interrupt request is acknowledged, or set by program
Set to 0 by program
Underflow
(Note 2)
(Note 2)
(Note 4)
(Note 6)
(Note 5)



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