R8C2K datasheet(150/471 Pages) RENESAS

150 / 471 page

R8C/2K Group, R8C/2L Group

15. Watchdog Timer

Rev.1.10

Dec 21, 2007

Page 133 of 450

REJ09B0406-0110

15.2

Count Source Protection Mode Enabled

The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection

mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the

watchdog timer.

Table 15.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled).

NOTES:

1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address

0FFFFh with a flash programmer.

2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI

bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address 0FFFFh with

a flash programmer.

Table 15.3

Watchdog Timer Specifications (with Count Source Protection Mode Enabled)

Item

Specification

Count source

Low-speed on-chip oscillator clock

Count operation

Decrement

Period

Count value of watchdog timer (4096)

Low-speed on-chip oscillator clock

Example: Period is approximately 32.8 ms when the low-speed on-

chip oscillator clock frequency is 125 kHz

Reset condition of watchdog

timer

• Reset

• Write 00h to the WDTR register before writing FFh

• Underflow

Count start condition

The WDTON bit(1) in the OFS register (0FFFFh) selects the operation

of the watchdog timer after a reset.

• When the WDTON bit is set to 1 (watchdog timer is in stop state

after reset)

The watchdog timer and prescaler stop after a reset and the count

starts when the WDTS register is written to

• When the WDTON bit is set to 0 (watchdog timer starts

automatically after reset)

The watchdog timer and prescaler start counting automatically after

a reset

Count stop condition

None (The count does not stop in wait mode after the count starts.

The MCU does not enter stop mode.)

Operation at time of underflow

Watchdog timer reset (Refer to 5.6 Watchdog Timer Reset.)

Registers, bits

• When setting the CSPPRO bit in the CSPR register to 1 (count

source protection mode is enabled)(2), the following are set

automatically

- Set 0FFFh to the watchdog timer

- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip

oscillator on)

- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is

reset when watchdog timer underflows)

• The following conditions apply in count source protection mode

- Writing to the CM10 bit in the CM1 register is disabled (It remains

unchanged even if it is set to 1. The MCU does not enter stop

mode.)

- Writing to the CM14 bit in the CM1 register is disabled (It remains

unchanged even if it is set to 1. The low-speed on-chip oscillator

does not stop.)

R8C2K датащи(PDF) 150 Page - Renesas Technology Corp

R8C2K датащи(HTML) 150 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL