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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STLC5466 датащи(PDF) 106 Page - STMicroelectronics |
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STLC5466 датащи(HTML) 106 Page - STMicroelectronics |
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106 / 130 page  STLC5466 106/130 2 CLOCK and TDMs TIMING 2.1 Synchronization signals delivered by the system For one of three different input synchronizations which is programmed, FSCG and FSCV* signals deliv- ered by the Multi-HDLC are in accordance with the figure hereafter: Figure 2-1: Clocks received and delivered by the Multi-HDLC tx Parameter T min. T typ T max Unit t1 Clock Period if 4096 kHz (3072) Clock Period if 8192 kHz (6144) 239 (320) 120 (158) 244 (325) 122 (162) 249 (330) 125 (165) ns ns t2 Delay between Clock A and Clock B - 60 0 +60 ns t3 Set up time Frame A/CLOCK A 10 t1-10 ns t4 Hold time Frame A (or B)/CLOCK A (or B) 10 t1-10 ns t4GCI Duration of Frame A (or B) 10 125000-(t1-10) ns t5 Clock ratio t5h/t5l 75% 100% 125% % t6 Duration of FSCG 488 (650) ns CLOCK A FRAME A or B 7 6 1 0 5 4 3 1) Sy Mode Bit3 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Time Slot 31 (if 2048 kbit/s) Time Slot 0 2) GCI Mode 3) V* Mode DIN 0/8, Echo D0UT 0/7, CB TDMO/7 FSCG delivered by the circuit FSC V* delivered by the circuit FRAME (A or B) FRAME A (or B) t1 t5h t5l t3 t4 t3 t4 t3 t4 GCI t2 CLOCK B If FS=FSCG Time Slot 23 (if 1536 kbit/s) t6 The four Multiplex Configuration Registers are at zero (no delay). |
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