ADE7569 datasheet(122/136 Pages) AD

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ADE7566/ADE7569

Preliminary Technical Data

Rev. PrA | Page 122 of 136

Table 138. SPI Interrupt Status Register SFR (SPISTAT, 0xEA)

Bit No.

Mnemonic

Default

Description

SPI Peripheral Busy Flag.

BUSY

Result

The SPI peripheral is idle.

BUSY

The SPI peripheral is busy transferring data in slave or master mode.

SPI Multi-Master Error Flag.

MMERR

Result

A multiple master error has not occurred.

MMERR

If the SS_EN bit is set, enabling the slave select input and asserting the SS while the SPI

peripheral is transferring data as a master, this flag is raised to indicate the error.

Write a 0 to this bit to clear it.

SPI Receive Overflow Error Flag. Reading the SPI2CRx SFR clears this bit.

SPIRxOF

TIMODE

Result

The SPI2CRx register contains valid data

SPIRxOF

This bit is set if the SPI2CRx register is not read before the end of the next byte

transfer. If the RxOFW bit is set and this condition occurs, SPI2CRx is overwritten.

SPI Receive Mode Interrupt Flag. Reading the SPI2CRx SFR clears this bit.

SPIRxIRQ

TIMODE

Result

The SPI2CRx register does not contain new data.

This bit is set when the SPI2CRx register contains new data. If the SPI/I2C

interrupt is enabled, an interrupt is generated when this bit is set. If the SPI2CRx

and the SS is deasserted.

SPIRxIRQ

The SPI2CRx register contains new data.

SPIRxBF

Status Bit for SPI Rx Buffer. When set, the Rx FIFO is full. A read of the SPI2CRx clears this flag

SPITxUF

Status Bit for SPI Tx Buffer. When set, the Tx FIFO is underflowing and data can be written into SPI2CTx.

Write a 0 to this bit to clear it.

SPI Transmit Mode Interrupt Flag. Writing new data to the SPI2CTx SFR clears this bit.

SPITxIRQ

TIMODE

Result

The SPI2CTx register is full.

The SPI2CTx register is empty.

SPITxIRQ

This bit is set when the SPI2CTx register is empty. If the SPI/I2C interrupt is

enabled, an interrupt is generated when this bit is set. If new data is not written

into the SPI2CTx SFR before the end of the current byte transfer, the transfer

stops, and the SS is deasserted. Write a 0 to this bit to clear it.

SPITxBF

Status Bit for SPI Tx Buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it.

SPI PINS

MISO (Master in, Slave out Data I/O Pin)

The MISO pin is configured as an input line in master mode

and as an output line in slave mode. The MISO line on the

master (data in) should be connected to the MISO line in the

slave device (data out). The data is transferred as byte-wide

(8-bit) serial data, MSB first.

MOSI (Master out, Slave in Pin)

The MOSI pin is configured as an output line in master mode

and as an input line in slave mode. The MOSI line on the master

(data out) should be connected to the MOSI line in the slave

device (data in).The data is transferred as byte-wide (8-bit)

serial data, MSB first.

SCLK (Serial Clock I/O Pin)

The master serial clock (SCLK) is used to synchronize the data

being transmitted and received through the MOSI and MISO

data lines. The SCLK pin is configured as an output in master

mode and as an input in slave mode.

In master mode, the bit rate, polarity, and phase of the clock are

controlled by the SPI Configuration Register SFR (SPIMOD1,

0xE8) and SPI Configuration Register SFR (SPIMOD2, 0xE9).

In slave mode, the SPI Configuration Register SFR (SPIMOD2,

0xE9) must be configured with the phase and polarity of the

expected input clock.

In both master and slave modes, the data is transmitted on one

edge of the SCLK signal and sampled on the other. It is important,

therefore, that the SPICPHA and SPICPOL bits are configured

the same for the master and slave devices.

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