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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST92F120JR6T датащи(PDF) 260 Page - STMicroelectronics |
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ST92F120JR6T датащи(HTML) 260 Page - STMicroelectronics |
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260 / 320 page  260/320 J1850 Byte Level Protocol Decoder (JBLPD) J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d) 10.8.6.3 DMA Management in Reception Mode The DMA in reception is performed when the RDRF bit of the STATUS register is set (by hard- ware). The RDRF bit is reset as soon as the DMA cycle is finished. To enable the DMA feature, the RXD_M bit of the IMR register must be set (by software). Each DMA request performs the transfer of a sin- gle byte from the RXDATA register of the peripher- al toward Register File or Memory Space (Figure 118). Each DMA transfer consists of three operations that are performed with minimum use of CPU time: – A load from the JBLPD data register (RXDATA) to a location of Register File/Memory addressed through the DMA Address Register (or Register pair); – A post-increment of the DMA Address Register (or Register pair); – A post-decrement of the DMA transaction coun- ter, which contains the number of transactions that have still to be performed. Note: When the REOBP pending bit is set (at the end of the last DMA transfer), the reception DMA enable bit (RXD_M) is automatically reset by hard- ware. However, the DMA can be disabled by soft- ware resetting the RXD_M bit. Note: The DMA request acknowledge could de- pend on the priority level stored in the PRLR regis- ter. Figure 118. DMA in Reception Mode JBLPD peripheral RXDATA Register File or Memory space Data received Previous data Current Address Pointer 9 |
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