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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST92F124 датащи(PDF) 222 Page - STMicroelectronics |
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ST92F124 датащи(HTML) 222 Page - STMicroelectronics |
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222 / 426 page  222/426 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.10 Interrupts and DMA 10.5.10.1 Interrupts The SCI can generate interrupts as a result of sev- eral conditions. Receiver interrupts include data pending, receive errors (overrun, framing and par- ity), as well as address or break pending. Trans- mitter interrupts are software selectable for either Transmit Buffer Register Empty (BSN set) or for Transmit Shift Register Empty (BSN reset) condi- tions. Typical usage of the Interrupts generated by the SCI peripheral are illustrated in Figure 116. The SCI peripheral is able to generate interrupt re- quests as a result of a number of events, several of which share the same interrupt vector. It is therefore necessary to poll S_ISR, the Interrupt Status Register, in order to determine the active trigger. These bits should be reset by the program- mer during the Interrupt Service routine. The four major levels of interrupt are encoded in hardware to provide two bits of the interrupt vector register, allowing the position of the block of point- er vectors to be resolved to an 8 byte block size. The SCI interrupts have an internal priority struc- ture in order to resolve simultaneous events. Refer also to Section 10.5.4 SCI-M Operating Modes for more details relating to Synchronous mode. Table 47. SCI Interrupt Internal Priority Receive DMA Request Highest Priority Transmit DMA Request Receive Interrupt Transmit Interrupt Lowest Priority 9 |
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