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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST90135 датащи(PDF) 140 Page - STMicroelectronics |
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ST90135 датащи(HTML) 140 Page - STMicroelectronics |
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140 / 190 page  140/190 ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) Bit 2 = CPHA: Transmission Clock Phase. CPHA controls the relationship between the data on the SDI and SDO pins, and the clock signal on the SCK pin. The CPHA bit selects the clock edge used to capture data. It has its greatest impact on the first bit transmitted (MSB), because it does (or does not) allow a clock transition before the first data capture edge. Figure 74 shows the relation- ship between CPHA, CPOL and SCK, and indi- cates active clock edges and strobe times. Bit 1:0 = SPR[1:0]: SPI Rate. These two bits select one (of four) baud rates, to be used as SCK. Figure 74. SPI Data and Clock Timing CPOL CPHA SCK (in Figure 74) 0 0 1 1 0 1 0 1 (a) (b) (c) (d) SPR1 SPR0 Clock Divider SCK Frequency (@ INTCLK = 12MHz) 0 0 1 1 0 1 0 1 8 16 128 256 1500kHz 750kHz 93.75kHz 46.87kHz (T = 0.67 µs) (T = 1.33 µs) (T = 10.66 µs) (T = 21.33 µs) 9 |
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