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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST90135 датащи(PDF) 131 Page - STMicroelectronics |
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ST90135 датащи(HTML) 131 Page - STMicroelectronics |
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131 / 190 page  131/190 ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) 9.4 SERIAL PERIPHERAL INTERFACE (SPI) 9.4.1 Introduction The Serial Peripheral Interface (SPI) is a general purpose on-chip shift register peripheral. It allows communication with external peripherals via an SPI protocol bus. In addition, special operating modes allow re- duced software overhead when implementing I2C- bus and IM-bus communication standards. The SPI uses up to 3 pins: Serial Data In (SDI), Serial Data Out (SDO) and Synchronous Serial Clock (SCK). Additional I/O pins may act as device selects or IM-bus address identifier signals. The main features are: s Full duplex synchronous transfer if 3 I/O pins are used s Master operation only s 4 Programmable bit rates s Programmable clock polarity and phase s Busy Flag s End of transmission interrupt s Additional hardware to facilitate more complex protocols 9.4.2 Device-Specific Options Depending on the ST9 variant and package type, the SPI interface signals may not be connected to separate external pins. Refer to the Peripheral Configuration Chapter for the device pin-out. Figure 64. Block Diagram n READ BUFFER SERIAL PERIPHERAL INTERFACE DATA REGISTER ( SPIDR ) POLARITY PHASE BAUD RATE MULTIPLEXER ST9 INTERRUPT TRANSMISSION END OF SPEN BMS ARB BUSY CPOL CPHA SPR1 SPR0 DATA BUS R254 INTCLK SERIAL PERIPHERAL CONTROL REGISTER ( SPICR ) R253 SDO SDI SCK/INT2 VR000347 10 INT2 INTERNAL SERIAL CLOCK TO MSPI CONTROL LOGIC INTB0 * * Common for Transmit and Receive 9 |
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