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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST723246 датащи(PDF) 128 Page - STMicroelectronics |
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ST723246 датащи(HTML) 128 Page - STMicroelectronics |
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128 / 161 page  ST72324 128/161 CLOCK CHARACTERISTICS (Cont’d) 12.5.5 Clock Security System (CSS) Note: 1. Data based on characterization results. 12.5.6 PLL Characteristics Operating conditions: VDD 3.8 to 5.5V @ TA 0 to 70°C 1) or V DD 4.5 to 5.5V @ TA -40 to 125°C Note: 1. Data characterized but not tested. Figure 69. PLL Jitter vs. Signal frequency1 The user must take the PLL jitter into account in the application (for example in serial communica- tion or sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the PLL jitter. Figure 69 shows the PLL jitter integrated on appli- cation signals in the range 125kHz to 2MHz. At fre- quencies of less than 125KHz, the jitter is negligi- ble. Note 1: Measurement conditions: fCPU = 4MHz, TA= 25°C Symbol Parameter Conditions Min Typ Max Unit fSFOSC Safe Oscillator Frequency 1) 3 MHz Symbol Parameter Conditions Min Typ Max Unit VDD(PLL) PLL Operating Range TA 0 to 70°C 3.8 5.5 V TA -40 to +125°C 4.5 5.5 fOSC PLL input frequency range 2 4 MHz ∆ f CPU/ fCPU Instantaneous PLL jitter 1) fOSC = 4 MHz. 1.0 2.5 % fOSC = 2 MHz. 2.5 4.0 % 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2000 1000 500 250 125 Application Signal Frequency (KHz) PLL ON PLL OFF |
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